Over 6+ years experience in Hardware Design, IP Core Development; heavy emphasis in the area of telecommunications and networking Knowledge in most communications protocols: 100 Mbps & 1G Ethernet, E1 and T1 telecom protocol, Wireless LAN 802.11 and SONET/SDH/PDH protocols. Knowledge in system integration and verification. Expertise in VHDL & Verilog design, functional verification, ASIC Synthesis, Timing closure, and FPGA Implementation. Knowledge in ASIC Design methodologies, VLSI Testing. High Speed digital design Knowledge of Low power design techniques. Knowledge of DFT techniques. Knowledge of project management and Quality Standards. FPGA project from concept to system integration and testing