• Physical Design : Cadene-IC, Virtuoso, Virtuoso-XL • Physical Verification: Assura, Calibre, Diva, Chameleon • Physical Verification Checks: DRC, LVS, Antenna, Latchup, ESD, IR-Drop. • Physical Extraction: Assura RCX, Calibre Extraction, Diva Extraction • Process :0.35um, 0.25um , 0.18um, 0.13um, 90nm, 45nm • Simulation(Post-Layout): Cadence Analog-Artist, Eldo, Spictre, TIspice • Operating Systems: Unix, Linux, Windows. • Full-Custom Layout of Integrated Circuit (Modules and chops) Analog Design and Full-Custom Layout of Integrated Circuit (Modules and chops) Routing optimization and post-layout simulations of power parts [Parasitic Resistances, IR drop and Electro-migration, using Assura et Calibre RCX] of models for Freescale Semiconductor: LDO Rsegulator, Charge pump, white-Led Driver, DCDC Convertes. PCU12.... * Design and routing optimization and post-layout simulations of power parts [Parasitic Resistances, IR drop and Electro-migration, using Assura and Calibre RCX] of models for different Texas-Instrument, Atmel, Connexant, Freescale Semiconductor and OnSemi technologies: LDO Regulator, Charge pump, white-Led Driver, DCDC Convertes. * Layout of Analogue Modules in different processes : TI/lbc7 [0.35um], TI/a035 [0.13um], TI/c021 [65nm], CSM [0.18um], TSMC [0.25um], TSMC [90nm], UMC [0.13um], ATML/at56khv [0.35um], ATML/at58khv [0.13um], LDO Regulator [Low Drop Out], Charge pump, White-Led Driver, DCDC Converters.