All Services Engineering & Architecture Design and front-end verification $9/hr · Starting at $25 To design and verify the design using HDLs like verilog, VHDL and SystemVerilog using QuestaSim. Work on FPGA using Vivado. About $9/hr · Ongoing Download Resume To design and verify the design using HDLs like verilog, VHDL and SystemVerilog using QuestaSim. Work on FPGA using Vivado. Skills & Expertise DesignFPGASystemVerilogVerilogVHDLVivado 0 Reviews This Freelancer has not received any feedback. Browse Similar Freelance Experts DesignersFPGA Developers