Design and front-end verification

Ms. Pooja Prabhakar Pise

Kolhapur, Maharashtra, India

Completed 45 days HEP training at Mentor Graphics, Bangalore based on digital design and verification using SystemVerilog. …Read More.

Engineering & Architecture

$9/hr Starting at $25

To design and verify the design using HDLs like verilog, VHDL and SystemVerilog using QuestaSim. Work on FPGA using Vivado.

$9/hr Ongoing

To design and verify the design using HDLs like verilog, VHDL and SystemVerilog using QuestaSim. Work on FPGA using Vivado.

DesignFPGASystemVerilogVerilogVHDLVivado