Digital RTL Design Engineer

Engineering & Architecture

$10/hr Starting at $35

Around 3 years of experience in design, implementation and verification of FPGA, ASIC and SoC digital systems. I am graduated in Mechatronics Engineer, now I am pursuing a Master’s Degree at University of Brasilia, Brazil, focused on Embedded Systems. Expertise: digital design, Verilog/VHDL, systemVerilog, C/C++ Tools: ModelSim, Altera Quartus, Cadence Incisive Simulator, Cadence First Encounter, Cadence Encounter RTL, Matlab, Simulink, National Instruments LabView, Microsoft Visual C++, Eagle PCB.

About

$10/hr Ongoing

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Around 3 years of experience in design, implementation and verification of FPGA, ASIC and SoC digital systems. I am graduated in Mechatronics Engineer, now I am pursuing a Master’s Degree at University of Brasilia, Brazil, focused on Embedded Systems. Expertise: digital design, Verilog/VHDL, systemVerilog, C/C++ Tools: ModelSim, Altera Quartus, Cadence Incisive Simulator, Cadence First Encounter, Cadence Encounter RTL, Matlab, Simulink, National Instruments LabView, Microsoft Visual C++, Eagle PCB.

Skills & Expertise

C++DesignDigital DesignEagle PCBEmbedded DevelopmentEmbedded SystemsEngineeringFPGALabVIEWMATLABMechatronicsMicrosoftPCB DesignRtlSimulinkSystems EngineeringTooling DesignVerilogVHDLVisual C++

Felipe Regis