Technical: ASIC/VLSI engineer, with 8+ years experience in chip design. Deep understanding of the entire RTL-to-GDSII flow. Hands-on experience in both front-end and physical design, using Synopsys tools and methodologies. Excellent knowledge of physical synthesis, STA and SI, DFT, low power design and optimization. Good knowledge of floor-planning, RC-extraction, LVS and DRC. Personal: Hard working and fully committed to the project. Excellent communication skills, both written and verbal. Have a good system understanding with "out of the box" strategies which lead to solving complex design and integration problems. A soul team player.