Cadence Vituoso Expert. Expert ''Analog IC Layout Design Engineer" , expertise in RF/ANALOG/DIGITAL layouts design. Worked on various foundries PDK'S i.e TSMC, Global foundry, SMIC on 40nm, 55nm, 65nm,150nm,180nm Technologies. Worked on WIFI IEEE 802.11a/b/g/n and BLUETOOTH chip , ADC/DAC/PLL/VCO/LDO/RX-Baseband/TX-Baseband/ SerDes etc... Efficient in various RF/Analog/Digital layout also having good knowledge of various Foudries PDK's. Expert in all physical verification checks like LVS, DRC, ERC, PEX, DFM and Antenna Used various techniques during layout for better performance i.e common centroid ,device matching,noise isolation and dummy devices, ESD protection ,Well proximity STI effects & Latch up protection. Make Padring and Run dummy fill for Top chip. Resolved complex issues independently Understanding of cutting edge silicon process technologies (CMOS Finfet 14nm) Worked on many projects successfully with Microchip ,TSMC ,Global Foundry. Also able to design and simulate various Analog and Digital circuits.i.e opamps Studied various reports given by TSMC and Global Foundry for highly optimized design with technology changes. Mentor and provide technical guidance to less senior layout designers. Ability to grasp new ideas and integrate them into desired results. Strong problem-solving, analytical, writing and communication skills.