Frontend VHDL/Verilog digital design eng (3896096)

Engineering & Architecture

Frontend VHDL/Verilog digital design eng

$15/hr Starting at $50

hold Master of Technology in VLSI Design from Malaviya National Institute of Technology Jaipur. My most recent experience is with VLSI Design working on Frond end and back-end. TECHNICAL SKILLS ? Languages: Basics of C, VHDL, Verilog, Perl. ? Operating System: Microsoft Windows 7, Red Hat Linux. ? Synopsys Tools: Design analyzer, Design compiler, HSPICE, Cosmoscope. ? Mentor Graphics: ? IC Nanometer Design - HEP 1 (Design Architect IC, IC Station, Calibre DRC, Calibre xRC, Eldo SPICE simulator ? Design, Verification & Test - HEP 2 FPGA Advantage, HDL Designer, Modelsim SE, Precision Synthesis, Leonardo Spectrum ASIC, ? Cadence : Virtuso(analog design), Encounter(ASIC Flow). ? Xillinx ISE: For FPGA Synthesis.

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$15/hr Ongoing

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hold Master of Technology in VLSI Design from Malaviya National Institute of Technology Jaipur. My most recent experience is with VLSI Design working on Frond end and back-end. TECHNICAL SKILLS ? Languages: Basics of C, VHDL, Verilog, Perl. ? Operating System: Microsoft Windows 7, Red Hat Linux. ? Synopsys Tools: Design analyzer, Design compiler, HSPICE, Cosmoscope. ? Mentor Graphics: ? IC Nanometer Design - HEP 1 (Design Architect IC, IC Station, Calibre DRC, Calibre xRC, Eldo SPICE simulator ? Design, Verification & Test - HEP 2 FPGA Advantage, HDL Designer, Modelsim SE, Precision Synthesis, Leonardo Spectrum ASIC, ? Cadence : Virtuso(analog design), Encounter(ASIC Flow). ? Xillinx ISE: For FPGA Synthesis.

Skills & Expertise

Analog Circuit DesignArchitectsBackendCompilerDesignDigital DesignFPGAFront End DevelopmentGraphic DesignLinuxMentoringMicrosoftPerlRed Hat Enterprise LinuxSkillSystems EngineeringTooling DesignVerilogVHDLVLSIWindowsWindows 7

rajesh sahu