During several years of study and work at Imperial College London as a PhD candidate and a post-doc researcher, and a 1.5 years of industrial experience in AccelerComm UK, I have been designing FPGA solutions and RTL models in various levels of abstraction and using several software tools. During my PhD, I have made RTL designs in VHDL, used Vivado HLS for high-level synthesis, and integrated different design compontents using Vivado. I have automated generating my high-performance FPGA solutions using Makelfiles and TCL scripts, which formed a fully-automated tool. The tool receives tree-based financial option pricing problems in simple C descriptions from the end-user, and automatically generates high-throughout FPGA systolic solvers. In my post-doc, I was part of a hardware-software project which enables per-kernel real-time slack measurement of OpenCL applications on FPGAs. On the hardware side, I completed an automated flow (in Python) which adds real-time slack measurement logic (in Verilog) into OpenCL HLS designs (in Quartus). On the software side, I have made an API in C (with a Python backend) which provides the end-user with C functions to read real-time slack values of different OpenCL kernels of the FPGA design. During my industrial experience at AccelerComm UK based in Southampton, I've had a range of experiences as part of the hardware teams to design and test channel coding solutions for 5G communication systems. My experiences include design of essential submodules, testing various sub/top -level modules, algorithmic modelling, documentation, and patent application writing.