All Services Engineering & Architecture Integrated Circuit Design $5/hr · Starting at $250 ASIC/FPGA Design flow: - executable specifications/behavioral model - RTL design and verification with Verilog/VHDL, - Synthesis/Timing analysis (Synopsys DC/PhysCompiler, PrimeTime) About $5/hr · Ongoing Download Resume ASIC/FPGA Design flow: - executable specifications/behavioral model - RTL design and verification with Verilog/VHDL, - Synthesis/Timing analysis (Synopsys DC/PhysCompiler, PrimeTime) Skills & Expertise AnalysisDesignDesign FlowMATLABRtlVerilogVHDLWriting 0 Reviews This Freelancer has not received any feedback. Browse Similar Freelance Experts Freelance WritersMATLAB ProgrammersManagement ExpertsDesignersC ProgrammersAlgorithm DevelopersC++ DevelopersPerl Developers