Principle EE w/30 Yr Experience in telecom, video, networking, storage industries
Hardware
FPGA based hardware design in both
Verilog and VHDL, IP based embedded systems development in Altera SOPC builder/Qsys suite,
schematic capture in Innoveda (ViewLogic), Cadence OrCad, Cadence Concept, Mentor VeriBest,
DxDesigner, AutoDesk Eagle, Layout in PADS, Eagle, Layout checking in Allegro, crosstalk/signal
integrity analysis using XTK, Digital (RTL) simulation via MTI (modelsim) Verilog/VHDL Simulator,
Board level simulation using LMC toolkit, Synthesis using Synopsis, Leonardo, Synplify synthesis
tools, back-end place and route (FPGA) using Xilinx XACT, Altera Quartus/SOPC builder, Altera
Max+2 NeoCAD/Foundry, Altera Max+2 and Xilinx XACT toolsets. Open source FPGA development
for Lattice devices via Linux based Icestorm toolset (Icarus/Odin ii/Yosys) as well as Lattice Diamond
(ne Neocad) based toolflow.
Software proficiencies: Embedded systems development (including hardware and functional
diagnostics) in various assembly languages as well as C targeting MicroC-OSII, VXWorks OS and
bare-metal. Skilled in the development of embedded systems code targeting Altera NiosII soft core
processors (Eclipse EDK), Atmel AVX microcontrollers, Motorola PowerPC and PowerQUICC
architectures. Proficient in the development and implementation of hardware (RTL) validation
strategies in C++.
Experienced in script development, modification and maintenance for both Windows and Unix/Linux
platforms in various shell /scripting languages (TCL, Perl, Python, etc).
Experienced in the following CAD/CAM design toolsets: Mastercam V8.0 2.5D, Mastercam V9.0 3D,
Mastercam X2SP2, Autocad, some SolidWorks exposure. Familiar with handwritten G-code for
milling.