Writing ECOs for fixing timing DRC, Clock Tran, Data tran, max cap and non clock cells. Handled one HM with 2M instance count, having 2 power domains (One collapsible and one non collapsible). Did multiple floorplan trails with DCG netlist in Innovus to achieve P&R convergence. Fix high resistance violations, Unconnect Instance, Missing vias based on GridCheck results on the FE db. Trial different run on Place to get the suitable recipe at Place. Implemented Midpoint point CTS to reduce latency and skew. Run FV/CLP checks on db & fix the FV issue Implemented dynamic fixes based on early PRO db on placement db. Ran STA, to generate. libs & analyze the timing. Fixing the DRCs Performed complete physical design activity starting from Netlist to GDSII. Placed macros based on communication and reduced notches. Tried different techniques to avoid congestion by applying blockages and padding. Built Clock Tree by meeting the targets. Wrote ECO’s in my design to meet Timing. Addressing signal EM by applying NDR on violating nets Fix the DRCs by opening the error marker in Caliber.