Senior Electrical Engineer, High Speed Design Specialist with long time experience in the field. I am committed to the ‘Engineering-on-demand’ alternative, in the High-Tech business arena, local to Silicon Valley. • High Speed Electrical Design including Signal Integrity and Power Integrity, Timing and Jitter budgeting for Flip-Chip IO Channels, Wirebonds devices and Multi-Core packages, related to Memory u-Controllers and Communications Processors devices • Technology involved are DDR2, DDR3, DDR4, LPDDR3; PCIe gen1, gen2, gen3; XAUI, SATA, 10GB Ethernet, plus multi-protocols SERDES, covering Serials, Parallel, GPIOs, and variety of Interface and Bus Protocols • Project tasks involving wide Parallel Data and Address Busses, up-to 2333 Mbps data-rate; simulation with Touchstone files reaching 200+ ports including power supply blocks ; Worst-case Analysis for near and far end Crosstalk in Odd and Even modes overlaid; Analysis of Worst-case Jitter and DynamicSkew, Eye Mask Characterization, Timing Set-up and Hold margin analysis • Project tasks involving Serial Data and Address Channels analyzed having Device Transmitters pre/de-Emphasis and receiver Equalization schemes, to improve BER or meet Standards/Protocols Eye Contour and bathtub plot specifications. Frequency Domain involving Differential S-parameters is performed, Common-Mode and Differential-Mode for Return and Insertion Losses are graphed and analyzed for their specific protocol mask requirements. Transmission Channel Tuning solution is seeked in-case of failure. Time Domain Analysis performed by running TDR simulati