Layout Design IGBT Power MOSFET IGBT Diode Superjunction Trench MCT Thyristor ESD Avalanche Photodiode Carrier Lifetime Ruggedness Radiation Photodiode PIN APD

A highly qualified, dedicated and driven semiconductor device engineer and scientist with extensive project management and device engineering experience.
Provide expert guidance to enhance product performance and reliability, performing product characterization and statistical data analysis.
Analyzing design and performance trade-offs to improve product yield and reliability.
Utilizing excellent project management and product engineering skills to successfully manage critical product yield improvement task forces and
identifying root causes for yield loses, proposing design and process solutions.

Technology interface to GLOBALFOUNDRIES (65G), TSMC (65LP, 40LP)
Analog ESD protection development for TSMC 40LP technology
Foundry PCM data analysis
High experience with layout design and optimization, process flow
Simulation experience with HSPICE, TCAD tools and environments, Unix design systems experience
ASIC design, RC extraction, timing analysis.
IC layout verification (DRC)
EDA tools for MEMS/NEMS design and analysis.
MOS Gated Power Devices
STI isolation, Trench refill

Implemented Projects:
Humidity Sensor (Integrated Capacitor), Pressure Sensor (Bulk Silicon orientation (110)
Trench Gate with Carrier Storage (CS) layer IGBT simulation and optimization.
ChemFET and enzyme - protein sensitive FET
Design and manufacturing BIB (Blocked Impurity Band) Photodetector for the 12-16 micron wavelength, 64x64 array, flip chip mounting with multiplexor, cooled T=10 K.
MOS controlled thyristor (2500V, 50 A)
Press Pack HV-IGBT (4500V, 40–1000A)
Solar Cells made with multisilicon wafers, 11.5% efficiency
Avalanche Photodiode simulation (3D Single Event Upset) and optimization
Semiconductor device models implemented with VHDL simulator
SJ MOSFET Devices (CoolMOS), special development – SJ MOSFET Avalanche Ruggedness, various die edge termination structures.
Junction Termination Extension Variation Lateral Doping (JTE VLD), own theoretical results in design optimization

Work Terms

Haves:
Physical semiconductor device simulation 2D,3D with results interpretation and design guidance.
Device and Chip Layout design with GDS output
Research report, scientific publications, references overview
Process Flow design and adjustment
Manufacturing supervising.

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