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Skills

  • Assembly Language
  • C
  • Embedded Systems
  • Java
  • Oracle
  • Oracle PL/SQL Development
  • PL/SQL
  • Programming
  • Rtos
  • SQL
  • Unix
  • VHDL

Services

  • Programmer & Data Analyst

    $9/hr Starting at $25 Ongoing

    Dedicated Resource

    Excellent Programming skills in C, Pyhton, PL/SQL (Oracle) and Unix Scripting. Hardware Synthesis skill (VHDL, SystemC) Embedded Systems: RTOS, Assembly Language

    Assembly LanguageCEmbedded SystemsJavaOracle

About

Working as a Graduate Research Assistant at TUC. Mar 2014 – Sep2014
My task is further development of specification tool “SpecScribe” which include addition, implementation and automation of Unified Power Format functionality to “SpecScribre” tool.

Technical Associate, Tech Mahindra Ltd. , Pune-India
Jun 2010 to Dec 2012
Tech Mahindra Limited is an Indian multinational provider of information technology (IT), networking technology solutions and business support services (BPO) to the telecommunications industry.

Project #2: Keep It Clean
Client: British Telecom Global Services (BTGS)
Work is to keep the data integrity in different Components of BTGS. I worked on Port entity and I found more than 3K discrepant Ports. Correcting single port result in 1800£ saving to BTGS.
Responsibilities:
?Writing PL/SQL code for finding discrepancy.
?Preparing report for client and higher management.
?Approach to components team and get the discrepancy removed.

Project #1: BT.COM (eCommerce)
Jun 2010 – Jun 2011
Client: British Telecom UK.
BT.com is ecommerce platform which brings all aspects of BT's products and services into a single platform. Maximize online services and transactions for BT.
Responsibilities:
?Web based Application Development for bt.com
?Re-skin, code refactoring and J-unit for “bt.com”.
?Product launch, Product configuration on “bt.com”.

Academic Projects:
Master’s Research Project
Oct 2013 – Mar 2014
Titled: “Concept and Implementation of SystemC Interface to Vhisyn”
Vhisyn is a tool designed to perform a high level synthesis of ITL (Interval Temporal Logic) hardware descriptions. VHDL is the only supported o/p format. In this project work, vhisyn is extended by an additional component providing functionality for export into SystemC.
?Python Introspection and Analysis of objects.
?Python script for Automatic RTL (Register Transfer Level) synthesis in SystemC.