i have 2+year experience as design and verification engineer and i have done 20+ industrial projects

ASIC/FPGA/SoC design and verificaion engineer
hi i have done more than 20 projects on UVM,systemverilog and verilog , VHDL
you can see some big projects below,
1s FUNCTIONAL VERIFICATION OF UNIVERSAL MEMORY CONTROLLER:-
Description:
Universal memory controller supports a variety of memory devices,
8 Chip selects, each uniquely programmable.
SDRAM,SSRAM, FLASH, ROM and many other devices supported.
It has feature like Burst transfers and burst termination
Industry standard WISHBONE SoC host interface
Responsibilities:
Analysis of the specification document.
Listing down feature.
Developing test plan.
Template environment coding of test-bench architecture.
Coding test-bench component and integration of them.
Connect different types of memory like SRAM.SDRAM, and FLASH to DUT.
Developing sanity test cases and functional test cases.
Functional and code coverage
Setting up regression and verification closure
HVL:- System Verilog Tool:- Questa sim 10.4e
2nd AHB Interconnect Functional Verification using UVM & System Verilog
Test plan development
Developing test bench architecture
Verification closure using Functional coverage & code coverage as closing criteria.
Methodology: UVM
3rd Development of AXI 3.0 VIP and validation using AXI slave VIP
Description:
AXI interconnect is configurable design for connecting multiple masters to multiple slaves.
Design also has a configuration interface for configuring slave address ranges.
As part of design verification we verified interconnect for different number of masters, slaves and slave address range configurations.
Responsibilities:
Test plan development
TECHNICAL SKILL
Developing test bench architecture coding
Verification closure using Functional coverage and Code coverage as closing criteria
HVL:- System Verilog Tool:- Questa sim 10.4e



skills;
Digital design
UVM
SystemC
System Verilog
Verilog
VHDL
UNIX
scripting PERL

Work Terms

work is more important than payment, if client not satisfied i not want money.