I am RTL Design Engineer and I am expert to design Verilog/Vhdl Code using Quartus, Xilinx ISE, Quartus and Modelsim and Dumping the code on the FPGAs
I am RTL Design Engineer and I have more than three years Industrial Experience in VLSI domain.
I am expert in
Designing any Digital Circuit using HDL or Schematic
write VHDL,Verilog code
Test bench for Verification and Simulation
Mealy/Moore Machine
Digital Electronics (K-Maps, Number System, Truth table,Combinational Ckt, Sequential Clt,Delay, Setup time, Hold Time etc)
Dumping On FPGA board.
Tools
Xilinx VIVADO, Xilinx ISE, Quartus , Model-Sim
FPGA
Basys 3 , DE2,DE10
Project Experience
ALU, Timer, 24 hrs Clock, Frequency divider,
MIPS , N bit Adder,N bit Subtraction, Design Different types of Controller, Design Data Path Etc.
Work Terms
I can do 16 hours work on a day and Generally my working time is 6 AM to 10 PM (Indian time). I will take 50 % advance before the work and will take 50 % after the work. I can communicate with the client by English/Hindi language.
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