Design of CMOS RF-Integrated Circuits

This is a project. do all part and make a professional report. please lock at #Requirements
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Part 1: Passive filter 
• Design a SE-SE high-pass filter to ‘capture’ 8 GHz wanted signal 
• Input and output port impedances: 50 Ω in parallel w/ 200 fF capacitance 
• ESD and pad model 
• Insertion loss/NF < 4 dB 
• In-band ripple <1 dB 
• Rejection at 6.425 GHz > 5 dB 
• Rejection at 5.8 GHz > 15 dB 
• Rejection at 5.1 GHz > 20 dB

Part 2: Amplifier
• Design a SE-SE multi-band low-noise amplifier (LNA) for 8 GHz
• Run dc, sp, trans, pss/hb, lssp, etc.
• Use of a transformer à bonus points!
• Specifications:
• Match to 50 Ω at the input w/ shunt parasitic capacitance of 50 fF (i.e., S_11 < -10 dB)
• S_21 > 15 dB
• Reverse isolation > 30 dB
• NF < 5 dB
• P1dB – max. achievable
• Power supply 1.2 V (nominal) 


#Requirements
• Draw schematic incl. interconnects
• Discuss design trade-offs!
• Provide detail (e.g., inductance and capacitance values of the components, length, width, L, C of the interconnects, area of each sub-block)
• Table of specifications and results
• Add graphs (e.g., S_21 (dB20 and phase) and S_11 (dB20), NF and group delay)
• Add graphs of inductor parameters (e.g., r_s, L, Q and self-resonance
frequency) for chosen dimension
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