All Services Engineering & Architecture ASIC Design / Verification Consultant $40/hr · Starting at $25 +15 years experience in ASIC and FPGA design and verification using: Matlab Verilog / SystemVerilog Cadence tools UVM Xylinx Altera About $40/hr · Ongoing Download Resume +15 years experience in ASIC and FPGA design and verification using: Matlab Verilog / SystemVerilog Cadence tools UVM Xylinx Altera Skills & Expertise ConsultantDesignFPGAMATLABSystemVerilogUvmVerilog 0 Reviews This Freelancer has not received any feedback. Browse Similar Freelance Experts ConsultantsDesignersMATLAB ProgrammersFPGA Developers