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Skills

  • Consultant
  • Design
  • FPGA
  • MATLAB
  • SystemVerilog
  • Uvm
  • Verilog

Services

  • ASIC Design / Verification Consultant

    $40/hr Starting at $25 Ongoing

    Dedicated Resource

    +15 years experience in ASIC and FPGA design and verification using: Matlab Verilog / SystemVerilog Cadence tools UVM Xylinx Altera

    ConsultantDesignFPGAMATLABSystemVerilog

About

More than one decade turning ideas into silicon and vice-versa

15+ years experience in ASIC design and verification for wireless communications, signal processing and image sensors, combining:
• system-level modeling knowledge (C++ / SystemC / SystemVerilog)
• extensive digital design experience, from ASIC architecture to RTL (Verilog/VHDL), through synthesis down to layout
• ASIC top level verification experience running directed timed gate-level simulations and constrained-random mixed-signal verification using Verilog-AMS / SystemVerilog/UVM (2 years experience designing from scratch a UVM testbench for mixed-signal ASICs).
Education

PhD in Electrical Engineering (Microelectronics), emphasis on Communications Systems VLSI design. IMEC, Belgium, assignment from Universidade de São Paulo, Brazil, June 2003.

MSc in Electrical Engineering (Microelectronics), emphasis on Communications Systems VLSI design. IMEC, Belgium, assignment from Universidade de São Paulo, Brazil, June 1998.

BSc in Electrical Engineering, Microelectronics. Universidade de São Paulo, Brazil, December 1995.

Languages: Portuguese (native), Spanish (bilingual), English (bilingual), French (advanced), Italian (basic), German (basic), Dutch (basic).


Some Highlights

5 successful tape-outs in the last 10 years, ranging from a 802.11n SoC transceiver to highly customized high-speed VsoCs (image sensors mixed-signal SoCs).

Father of the collision-free interleaver, widely deployed in turbo codes in 3G, 4G. Patent: “A method and apparatus for interleaving, deinterleaving”, A. Giulietti, V. Derudder, B. Bougard, M. Thul, J.U. Giese, G. Cosgul, EP1267511. Original paper: “Parallel turbo coding interleavers: avoiding collisions in accesses to storage elements” (144 citations).

Books: A. Giulietti, B. Bougard, L. Van der Perre, “Turbo codes: designable and desirable”, Springer, 2003. ISBN 1-4020-7660-6.

Cadence User Conference (CDNLive EMEA) participations as speaker in 2016 and 2017: “Image Sensor Design and Verification Challenges".

Work Terms

Up to 40 hours/week depending on the project schedule; e-mal communication preferred.