9+ years of experience in the Hardware front-end domain, ASIC/FPGA/Emulation IP design and verification. Degrees: MSc, BSc, Electronis design systems. Keywords: Verilog, System Verilog, C++, System C , VMM/UVM, SVA, CDV, CRT, EDA tools, Perl csh, Makefile, test plan, System Architect, Synthesis. IC, IP, ASIC, FPGA, Emulation.