Operating System: Windows10, Ubuntu, VNC server on Linux using vim/gvim editor HDL-HVL Languages: Verilog, basic VHDL, System Verilog, UVM Domain: ASIC/FPGA Design Flow, Digital Design and verification methodologies Knowledge: RTL coding, FSM based design, Testbench Coding, Simulation, Code Coverage, and Functional Coverage EDA Tool: Incisive Enterprise Simulator NC-Verilog, QuestaSim , Modelsim, Verdi and ISE, VCS, Xilinx ISE, DVE