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Engineering & Architecture Math / Science / Algorithms

RTL (FPGA/ASIC) design engineer

$45/hr Starting at $100

> RTL

>Verilog, VHDL, SystemVerilog

> Digital Designer

> Networking protocols(TCP, UDP etc)

> Ethernet Communication (1G, 10G Systems)

> DDR2, DDR3, GMII, PCIe

> Serial Communication Protocols( UART,SPI,I2c)

> Computation 

> High Frequency Trading System 

> Compression 

> Encodings, Encryptions

> System Design


About

$45/hr Ongoing

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> RTL

>Verilog, VHDL, SystemVerilog

> Digital Designer

> Networking protocols(TCP, UDP etc)

> Ethernet Communication (1G, 10G Systems)

> DDR2, DDR3, GMII, PCIe

> Serial Communication Protocols( UART,SPI,I2c)

> Computation 

> High Frequency Trading System 

> Compression 

> Encodings, Encryptions

> System Design


Skills & Expertise

AlgorithmsCommunication ProtocolsComputational ModelingDigital Signal ProcessingFPGANetworkingVerilogVHDL

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