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Skills

  • Algorithms
  • Communication Protocols
  • Computational Modeling
  • Digital Signal Processing
  • FPGA
  • Networking
  • Verilog
  • VHDL

Services

  • RTL (FPGA/ASIC) design engineer

    $45/hr Starting at $100 Ongoing

    Dedicated Resource

    RTL Verilog, VHDL, SystemVerilog Digital Designer Networking protocols(TCP, UDP etc) Ethernet Communication (1G, 10G Systems) DDR2, DDR3, GMII, PCIe Serial Communication Protocols( UART,SPI,I2c)...

    AlgorithmsCommunication ProtocolsComputational ModelingDigital Signal ProcessingFPGA