Banner Image

All Services

Engineering & Architecture engineering (mechanical / chemical / civil / electrical)

Verification engineer

$10/hr Starting at $25

coding for SOC devices

using System Verilog and UVM.

Digital design using HDL's(Verilog and VHDL)

HVL's: SV, UVM

HDL: Verilog, VHDL

programming: C,C++

shell scripting(bash)

version control tools: Cleartool

software's/simulators: Vivado(Xylinx),Questsim(Siemens),Modelsim,Isim(cadence),iccarus verilog(open source)

About

$10/hr Ongoing

Download Resume

coding for SOC devices

using System Verilog and UVM.

Digital design using HDL's(Verilog and VHDL)

HVL's: SV, UVM

HDL: Verilog, VHDL

programming: C,C++

shell scripting(bash)

version control tools: Cleartool

software's/simulators: Vivado(Xylinx),Questsim(Siemens),Modelsim,Isim(cadence),iccarus verilog(open source)

Skills & Expertise

EngineeringSystem VerilogUvmVerilogVHDL

0 Reviews

This Freelancer has not received any feedback.

Browse Similar Freelance Experts

Engineers