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Skills

  • Engineering
  • System Verilog
  • Uvm
  • Verilog
  • VHDL

Services

  • Verification engineer

    $10/hr Starting at $25 Ongoing

    Dedicated Resource

    coding for SOC devices using System Verilog and UVM. Digital design using HDL's(Verilog and VHDL) HVL's: SV, UVM HDL: Verilog, VHDL programming: C,C++ shell scripting(bash) version control tools: Cleartool...

    EngineeringSystem VerilogUvmVerilogVHDL

About

Passionate verification engineer

hi,
I am 27. working as a verification engineer.
with 2+ years of experience with system Verilog
1 year of experience with UVM.

Programming languages: C, C++
Hardware description languages: Verilog,VHDL
HVL: System Verilog, UVM(universal verification methodology)

Verification projects include:
1.)FIFO with ready valid protocol
this project was verified using UVM methodology with 1000,5000+ transactions
complete testing with multiple tests.
implemented in Xilinx vivado.
2,) RAM SOC project
This project was verified using UVM methodology with 1000,5000+ transactions
complete testing with multiple tests.
implemented using Questasim.

Work Terms

I can work 5-6 hours per day/ 30 hours weekly

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